The present invention relates generally to a memory device and fabrication of the same. More particularly, the present invention relates to a flash memory device, and a mask for fabricating the same.
The demand for semiconductor memory that is electrically programmable and erasable and that can retain stored information when not powered is growing. Flash memory is an electrically erasable programmable read only memory (EEPROM) that is widely used as a nonvolatile memory, that is, a memory capable of retaining stored information when power is interrupted.
Further, high-integration technology is constantly being developed in an attempt to develop large-capacity memory devices capable of storing a large quantity of data in increasingly limited space. For this, a NAND type flash memory device has been proposed in which a plurality of memory cells are serially connected to form a single string and a plurality of the strings constitute a single memory cell array.
A flash memory cells of a NAND flash memory device includes a current pass formed over a semiconductor substrate between a source and a drain, and further includes a floating gate and a control gate formed over the semiconductor substrate. An insulator is interposed between the floating gate and the control gate.
During a typical programming operation of a flash memory cell, the source of the memory cell and the semiconductor substrate (i.e., a bulk region) are first grounded. A positive high voltage (program voltage: VPP, for example 15V to 20V) is applied to the control gate, and a voltage for programming (for example, 5V to 6V) is applied to the drain of the memory cell, in order to generate hot carriers. The hot carriers are generated as electrons in the bulk region accumulate on the floating gate due to the electric field of the high voltage VPP applied to the control gate, and as charges supplied to the drain are continuously accumulated.
The erasing operation of a flash memory cell is simultaneously performed for flash memory cells in a sector unit sharing a bulk region. The erasing operation is performed by applying a negative high voltage (erase voltage: Vera, for example −10V) to the control gate and applying a given voltage (for example, 5V) to the bulk region to cause Fowler-Nordheim tunneling (F-N tunneling). The F-N tunneling causes the electrons accumulated on the floating gate to be discharged toward the source (that is, electrons tunnel from the floating gate to the source) so that the flash memory cells have an erase threshold voltage that ranges from about 1V to 3V.
In other words, the programming operation increases the threshold voltage of a cell transistor by causing channel hot electrons to jump onto (i.e., accumulate on) the floating gate; and the erasing operation of the flash memory cell lowers the threshold voltage of the cell transistor by generating a high voltage between the source/the substrate and the floating gate to discharge the electrons accumulated on the floating gate.
However, flash memory has problems such as bridge generation between drain contacts, instability of electrical distribution characteristics between the source contact of the source region and the drain contact of the drain region, and the like.